The present invention relates, in general, to semiconductor devices, and more particularly, to a novel method of planarizing the surface of a semiconductor device.
As semiconductor active geometries shrink to submicron levels, there is an increased need for tightly spaced high density metallization to interconnect all the elements that can be implemented on a submicron semiconductor device. One parameter limiting the density and spacing of conductors on a semiconductor device is planarity of the surface on which the conductors are constructed. Previous methods of planarizing inner layer dielectrics generally could not provide surface excursions of less than 2000 angstroms (.ANG.) which was required for the tightly spaced conductors. Both wet and dry (plasma) etching of the dielectric portions that were covering tightly spaced conductors were limited by gaps or spaces between the dielectric features to be planarized. If the gaps were too small, the portion of the mask that was covering the gap would lift-off during the planarization etch procedures. Mask lift-off resulted in inadvertent etching of areas that were to be protected by the mask. Often, the portion of the mask that lifted-off settled on another area of the dielectric and blocked etching of that area.
Wet etching of dielectrics that were covering narrow conductors was also limited by the inability of the wet etch to penetrate the gaps and for the etch byproducts to diffuse away from the gaps.
Accordingly, it is desirable to have a method of planarizing semiconductor device surfaces that provides a surface with excursions of less than 2000 .ANG., that does not lift-off the mask during the etching process, and that properly etches small areas between closely spaced features.